View TDA7529_1758529.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

march 2007 rev 1 1/60 1 TDA7529 rf front-end for am/fm dsp car-radio with if sampling features fully integrated vco for world tuning high performance pll for fast rds system i/q mixer for fm if 10.7mhz with image rejection and integrated lna i/q mixer for am if 10.7mhz up conversion with high dynamic range integrated balun, which allows saving of external mixer tank rf agc, if agc, dagc low noise if amplifier with switched wide dynamic agc range if switch for fm / am / iboc electronic alignment for the preselection stages i 2 c/spi controlled single 5v supply alternative frequency control signals to dsp description the front-end is a high performance tuner circuit for am/fm - dsp car-radios with 10.7mhz if sampling. it contains mixer and if amplifiers for am and fm, fully integrated vco and pll synthesizer on a single chip. use of bicmos technology allows the implementation of several tuning functions and a minimum of external components. lqfp64 table 1. device summary part number package packing TDA7529 lqfp64 exposed pad (10x10x1.4) tray TDA7529tr lqfp64 exposed pad (10x10x1.4) tape and reel www.st.com
contents TDA7529 2/60 contents 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 imr mixer and active balun output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 fm rf-agc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 am rf-agc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 if agc and if amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 d/a converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 vco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 fref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.10 gpio - general purpose io interface pins . . . . . . . . . . . . . . . . . . . . . . . . 16 3.11 afsample/afhold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.12 serial bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 general key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 fm - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 am - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6 if - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7 vco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.9 dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.10 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.11 phase frequency detector and charge pump . . . . . . . . . . . . . . . . . . . . . . 25 4.12 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.13 d/a-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TDA7529 contents 3/60 4.14 a/d-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.15 gpio ? general purpose io interface pins . . . . . . . . . . . . . . . . . . . . . . . . 27 4.16 afsample / afhold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.17 serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 tuning state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 tuning state machine modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.1 mode 000: buffer (nil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.2 mode 001: preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.3 mode 010: search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.4 mode 011: af update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.5 mode 100: jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 mode 100: check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 mode 110: load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 mode 111: end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 register swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 state machine start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.1 short_reg (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 adcctrl (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.3 gpio mode (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.4 agc and mixer control (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1.5 register (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.6 divider r (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.7 if agc control (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.8 fm agc (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.9 agc voltage threshold (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1.10 mixer alignment 1 (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1.11 mixer alignment 2 (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.12 pll control 1 (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.13 pll control 2 (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.14 pll test (13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.15 misc 2 (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.16 wait lock (15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
contents TDA7529 4/60 6.1.17 agc time constant settings (16 / 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.18 amagc control (17 / 33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.19 gpio output level control (18 / 34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.20 if control (19 / 35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.21 af state machine wait time 1 (20 / 36) . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.22 pll main divider (n-divider) 1 (21 / 37) . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.23 pll main divider (n-divider) 2 (22 / 38) . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.24 pll main divider (n-divider) 3 (23 / 39) . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.25 pll divider ratio calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.26 vco divider (v-divider) (24 / 40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.27 charge pump current (25 / 41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.28 tuning dac 1 (26 / 42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.29 tuning dac 2 (27 / 43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.30 dac output voltage = 600mv + dacval * 9mv . . . . . . . . . . . . . . . . . . . 53 6.1.31 different controls (28 / 44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.32 misc 3 (29 / 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.33 analog test select (30 / 46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.34 ad converter test (31 / 47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.35 read 1 (48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.36 read 2 (49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
TDA7529 list of tables 5/60 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. if agc and if amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. switching frequency as a function of the process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. gpio - general purpose io interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. supports data communication using the spi and the i 2 c protocol . . . . . . . . . . . . . . . . . . . 17 table 7. i 2 c addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. general key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11. fm - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. am - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13. if - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. vco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 17. phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 18. phase frequency detector and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 19. temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 20. d/a-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 21. a/d-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 22. gpio - general purpose io interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 23. afsample / afhold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 24. serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 25. values of the programmable wait times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 26. short_reg (0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 27. adcctrl (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 28. gpio mode (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 29. agc and mixer control (3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 30. register (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 31. divider r (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 32. if agc control (6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 33. fm agc (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 34. agc voltage threshold (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 35. mixer alignment 1 (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 36. mixer alignment 2 (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 37. pll control 1 (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 38. pll control 2 (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 39. pll test (13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 40. misc 2 (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 41. wait lock (15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 42. agc time constant settings (16 / 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 43. amagc control (17 / 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 44. gpio output level control (18 / 34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 45. if control (19 / 35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 46. af state machine wait time 1 (20 / 36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 47. pll main divider (n-divider) 1 (21 / 37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 48. pll main divider (n-divider) 2 (22 / 38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
list of tables TDA7529 6/60 table 49. pll main divider (n-divider) 3 (23 / 39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 50. pll divider ratio calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 51. vco divider (v-divider) (24 / 40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 52. charge pump current (25 / 41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 53. tuning dac 1 (26 / 42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 54. tuning dac 2 (27 / 43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 55. different controls (28 / 44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 56. misc 3 (29 / 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 57. analog test select (30 / 46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 58. ad converter test (31 / 47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 59. read 1 (48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 60. read 2 (49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 61. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
TDA7529 list of figures 7/60 list of figures figure 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. positive current diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. positive/negative current diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. voltage and current mode with hand-over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. i 2 c (sub address mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. preset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. search timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10. af update timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11. jump timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12. check timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. load timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14. end timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 15. buffer/control serial bus sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16. registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 17. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 18. lqfp64 (10x10x1.4mm) exposed pad down mechanical data and package dimensions (exposed pad size for d2 and e2: 4.5mm max.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
functional block diagram TDA7529 8/60 1 functional block diagram figure 1. functional block diagram agc div :n vco pll div agc supply bus interface agc i q 2 tv1 if 10.7mhz fm am 2 2 fref tv2 fm am iboc q i 2 wx 2 dagc msb/lsb af update afhold afsample i2c spi ac00038
TDA7529 pins description 9/60 2 pins description figure 2. pin connection table 2. pin assignment pin # pin name description 1 balun1 active balun input 1 2 balundec active balun input 2 (de coupling) 3 dac2 tuning dac 2 output 4 dac1 tuning dac 1 output 5 fmmix1in fm mixer input ? high gain stage = mode 1 6 fmmix1dec fm mixer de couple 7 fmagc2/gp7 fm agc voltage output / alternative gp7 output 8 fmagc1 fm pin diode driver output 9 fmmix2in fm mixer input ? low gain stage = mode2 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 54 55 53 52 51 50 49 43 42 41 39 38 40 48 47 46 44 45 fmmix1dec fmmix1in dac1 balundec balun1 dac2 gndrf1 fmmix2dec fmmix2in fmagc2/gp7 fmagc1 vccrf1 vcodec1 vtune vcodec2 lflc gndvco lfhc gndpll vccpll gp1 gndro gndrf2 gp5 ifin2 gp2 biasd1 ifin2 ifin3 vccif ifin4 ifdec tcif2 vdddec vccbus miso clk cs/as mosi gndif tcif1 ifout1 biasd2 ifout2 ac00039 22 23 24 25 26 60 tcam 61 tcfm 62 vccrf2 63 balunout1 64 balunout2 ifag2 gp4/vds amagc2/gp8 afhold afsample 17 18 19 20 21 37 36 34 33 35 ps busgnd xtalo xtali vccro 12 13 14 15 16 ifagc1 mixbiasdec ammixin amagc1 ammixdec
pins description TDA7529 10/60 10 fmmix2dec fm mixer de couple 11 gndrf1 gnd rf1 section 12 amagc1 amagc pin diode driver output 13 ammixdec am mixer de couple 14 ammixin am mixer input 15 mixbiasdec mixer bias de coupling 16 ifagc1 ifamp gain control via ifagc - lsb 17 ifagc2 ifamp gain control via ifagc - msb 18 gp4/vds gpio 4 / vds input 19 amagc2 / gp8 amagc voltage output / alternative gp8 output 20 afhold af state machine hold output 21 afsample af state machine sample output 22 vccrf1 supply rf1 section 23 vcodec1 bias de couple for vco 24 vtune vco tuning voltage 25 vcodec2 bias de couple for vco 26 gndvco vco ground 27 lflc loop filter low current output 28 lfhc loop filter high current output 29 gndpll pll ground 30 vccpll supply pll 31 gp1 gpio 1 32 gndro ground pll digital part 33 xtali reference oscillator input 34 xtalo reference oscillator output 35 vccro supply pll digital part 36 busgnd businterface ground 37 ps protocol select 38 cs/as chip select / address select 39 clk spi / i2c clodk 40 mosi spidata input / i2c data 41 miso spi data output 42 vccbus supply of businterface 43 vdddec de couple of internal 3.3v (=3,3v + vbe) table 2. pin assignment (continued) pin # pin name description
TDA7529 pins description 11/60 44 biasd2 de coupling for biasing 45 ifout2 differential if output 2 46 ifout1 differential if output 1 47 tcif1 time constant if agc for am 48 gndif ground if section 49 tcif2 time constant if agc for fm 50 ifdec de couple of if amplifier 51 ifin4 if input 4 52 vccif supply if section 53 ifin3 if input 3 54 biasd1 de coupling for biasing 55 ifin2 if input 2 56 gp2 gpio 2 57 ifin1 if input 1 58 gp5 gpio 5 59 gndrf2 gnd rf2 section = active balun gnd 60 tcam am agc time constant 61 tcfm fm agc time constant 62 vccrf2 supply voltage rf2 section 63 balunout1 active balun output 2 = fm output 64 balunout2 active balun output 1 = am output table 2. pin assignment (continued) pin # pin name description
function description TDA7529 12/60 3 function description 3.1 imr mixer and active balun output the imr mixer has two fm inputs (referred as mode 1 / mode 2) and one am input selectable by software. the fm inputs differ by their gains, noise figures, iip3 and maximum signal handling capability. the mode 1 fm input (with the hi gher gain, lower iip3 and lower noise figure) is normally coupled with passive antenna input stages; the mode 2 fm input is normally used for input stages featuring an external preamplifier. there are two single ended outputs of the imr mixer: balunout1 has a 4 db higher gain than balunout2. it is not recommended to use both outputs in parallel. the balun1 pin is the current mixer output over an internal resistor. the lc filter at balun1 can be realized with a lo w cost smd-coil (q ~ 4). 3.2 fm rf-agc the fm agc system is controlled by a peak detector, whose gain can be varied by the keyed agc. the latter function is meant to be controlled by a d/a converter in the back-end part of the system. the time constant of the fm rf-agc is defined by an external capacitor connected to tcfm and programmable internal currents. the currents can be selected independently for agc attack and decay. by this the ratio between the attack and the decay time can be programmed between 0.4 and 250. the fm rf-agc has two output pins to drive one pin diode attenuator and the external preamplifier gain control. the agc outputs can be programmed to the following modes: 1. positive current i=f(e): after reaching the agc threshold voltage, the current output delivers a current i=f(e) up to 15ma in a voltage range from 0.1v (@10a sink current) up to v cc -1.2v with a quasi-exponential characteristic referred to the voltage at tcfm. figure 3. positive current diagram 2. pos/neg current i = f(e): below the agc threshold voltage the agc output sinks a constant current of -5 ma. when the rf input level crosses the agc threshold voltage, the current is reduced down to 0 ma with a quasi-logarithmic behavior. at half control voltage the current becomes positive and reaches up to 15ma following an exponential function. v_tcfm iout 15ma f(e) current ac0004 0
TDA7529 function description 13/60 figure 4. positive/negative current diagram 3. constant current mode: the output current can be set to 2 ma source current. the agc detector is in power -down mode and only the pin diode driver is active. 4. voltage and current mode with hand-over: the vthr level is programmable with 6 bit in the range of 0.2v to 2.56v. the voltage vthr is the internal reference voltage of an external cascode transistor emitter feedback loop. figure 5. voltage and current mode with hand-over the voltage output swing is comprised between 0v and 3.3v (vdd). the microcontroller can read the voltage at the agc capacitor via the serial control interface. 3.3 am rf-agc the am agc system is controlled by an average detector. the time constant of the am rf- agc is defined by an external capacitor connected to tcam and programmable internal currents with symmetrical attack/decay behavior. the am rf-agc has two output pins to drive one pin diode attenuator and the external preamplifier gain control. the agc outputs can be programmed to the same modes as the fm rf-agc with the exception of pos/neg current. the microcontroller can read the voltage at the agc capacitor via the serial control interface. 1.65v iout 15ma f(e) current ac00041 iout vout vthr vthr ac00042
function description TDA7529 14/60 3.4 if agc and if amplifier the if agc system is controlled in am with an average detector and in fm with a peak detector, and reduces the mixer gain. the time constant is defined by two external capacitors connected to tcif1 and tcif2 respectively, and programmable internal currents. the microcontroller can read the voltage at the agc capacitors via the serial control interface. the if amplifier gain is not affected by the on-chip if-agc but is meant to be controlled by the back-end part of the system through pins ifagc1 and ifagc2. the gain is reduced in 6 db steps starting from the programmed value "g" according to the following table: 3.5 dividers the mixer divider v is followed by a divide-by-4-stage that generates 0/90/-90 lo signals for the imr mixer (90/-90 mode to switch between upper or lower side-band suppression in the imr mixer). the main divider n can be operated in integer mode. 3.6 d/a converters the front-end contains two d/a-converters for tuning the filters of the fm pre-stage. the converters have a resolution of 9 bit. table 3. if agc and if amplifier ifagc2 ifagc1 gain 00g 0 1 g - 6db 1 1 g - 12db 1 0 g - 18db
TDA7529 function description 15/60 3.7 vco the 3.7 ghz vco has an internal switch that allows extending th e oscillation frequency range. this is required by the fact that each of the two resulting vco sub-bands (upper/lower) cannot individually cover the complete required frequency range versus temperature and process; for this reason a calibration procedure is needed to determine the process type (typical, slow, fast) and select the transition frequency between the two vco sub-bands. to run the procedure the vco range 2 must be selected, the synthesized frequency needs to be set to 4ghz; then if vtuning > 2.6v then the process is 'slow', if vtuning < 1.7v then is 'fast' and otherwise is 'typical'. the switching frequency as a function of the process is reported in the following table: 3.8 fref the reference frequency for the pll can be derived by a xtal directly connected to the device or by means of an lvds signal. in the latter case an external matching resistor must be used to obtain the desired input signal level. 3.9 a/d converter the front-end contains a 6 bit sar a/d-converter for sensing several analog values of the tuner. the following analog sources can be switched to the adc input by software command: fm rf agc capa citor voltage am rf agc capacitor voltage if agc capacitor voltage (automatically connected to the fm or am if agc filtering capacitor) pll tuning voltage temperature sensor gpio 1 voltage gpio 2 voltage adc reference generated from vcc. the adc can be clocked by an integrated rc -oscillator, in which case the oscillation frequency is programmable, or by the pll reference frequency. table 4. switching frequency as a function of the process slow typ fast 3.635ghz 3.72ghz 3.794ghz
function description TDA7529 16/60 3.10 gpio - general purp ose io interface pins the front-end has seven gpio - general purpose control pins to switch external stages (output), e.g amplifiers, or to read the status of external stages (input), e.g. control voltages. some control pins are multiplexed with other functions that are not necessary in every tuner design (fm agc keying, am cascode control). all the gpios may put in tristate or in enable mode. when in enable the gpios can be configured as shown in the following table. all gpios are short-circuit protected by current limiter and voltage-tolerant up to 3.5v. table 5. gpio - general purpose io interface pins gpio ports function gpio1 selects function of gpio 1: if input, connects gpio1 to adc (adc must then be configured to use gpio1 as input); if output, level depends on gpio out lev ctrl gpio1 - anlgin to ad - digout gpio2 selects function of gpio 2: if input, connects gpio2 to adc (adc must then be configured to use gpio2 as input) and to kagc (fm kagc must then be enabled); if output, level depends on gpio out lev ctr gpio2 - anlgin to ad ? kagc in - digout gpio4 selects function of gpio4: if input, configures gpio4 as am cascode v ds input; if output, level depends on gpio out lev ctrl gpio4 - anlgin - digout gpio5 selects function of gpio5: if input, it is directly connected to read-only register byte 48 bit 4; if output, level depends on gpio out lev ctrl gpio5. when set to input, it is necessary to set if amp gpio5 out mode to ?on gpio5 out en? (labels are wrong). also used for production testing as analog output (not relevant for application). - digin - out (dig or anlg) gpio6 selects function of gp io6 if device is configured in i 2 c mode: if input, it is directly connected to read-only register byte 48 bit 5; if output, level depends on gpio out lev ctrl gpio5. when the device is configured in spi mode, program gpio out lev ctr gpio5 to ?low?. the value of gpio mode gpio5 does not matter - din (spi miso out) - dout (spi miso out) gpio7 selects function of gpio7: if digital output is selected, level depends on gpio out lev ctrl gpio7; otherwise, co nfigures gpio7 as fm agc vout - digital out - fm agc vout gpio8 selects function of gpio 8: if output, level depends on gpio out lev ctrl gpio8; otherwise, configures gpio8 as am agc vout - digital out - am agc vout
TDA7529 function description 17/60 3.11 afsample/afhold on the TDA7529 there are two dedicated open drain pins (afsample and afhold), that allow the control of the dsp (mute and quality controls) during af update. details are given in chapter 5 . 3.12 serial bus interface the TDA7529 has a serial data port for communication with the microcontroller. it is used for programming the device and for reading out its detectors. this port supports data communication using the spi and the i 2 c protocol. the data transfer of several consecutive bytes is supported by the auto increment feature. the "ps"- pin (protocol select) determines which communication protocol is used. the information is not latched, so any level change at this pin immediately affects the protocol used by the TDA7529. the spi protocol is selected by setting ps = 0 while, during the i 2 c operation, ps needs to be open (internally set to 1). spi-protocol: cpol=1, cpha=1. the cs pin performs the chip select function during the spi operation; it has to be reset to 0 during transmission or reception, otherwise set to 1 (the cs pin is set to 1 by leaving it open). both the cs and the as functions are performed by the cs pin. when the i 2 c mode is used, the "as" pin determines which i 2 c address or group of addresses (see below) is used. three different external connections are defined to represent three groups of addresses (refer to the following table for details). the information is not latched, so any level change at this pin immediately affects the address used by the TDA7529. first the ic address is transmitted including the r/w bit for setting the direction of the following data transfer table 6. supports data communication using the spi and the i 2 c protocol pin spi signal pin i 2 c signal signal 1 ps protocol select spi/i 2 c ps protocol select spi/i 2 c signal 2 cs chip select as address select signal 3 clk clock clk clock signal 4 mosi master out ? slave in data bidirectional data signal 5 miso master in ? slave out gp6 general purpose out
function description TDA7529 18/60 x = must be "0" for reading, can be "1" or "0" for writing to the TDA7529 d = determinates the direction of data transfer, reading or writing r / w = indicates the address to read to and/or to write from a single TDA7529 w = indicates those addresses that can be used to transmit equal data to several TDA7529 frontends. a read out has no purpose for these addresses (data collision), but must be possible without damaging the tuner ic. the two serial bus protocols, i 2 c and spi, are as follows: figure 6. i 2 c (sub address mode) figure 7. spi data auto increment mode is always active regardless of the serial bus mode chosen. table 7. i 2 c addresses tuner: tuner 3 tuner 2 tuner 1 level at pin as 2.2v ? 3. 5v 1.1v ? 1.7v 0.0v ? 0.6v address: 1100 1xxd 1100 x1xd 1100 xx1d msb ... lsb 1100 000d 1100 001d r / w 1100 010d r / w 1100 011d w w 1100 100d r / w 1100 101d w w 1100 110d w w 1100 111d w w w 7107107 07 0 r/w sm x 4th byte data byte n+1 address 1st byte 2nd byte subaddress n 3rd byte data byte n ac0004 3 7107 07 07 0 sm r/w 4th byte data byte n+2 1st byte subaddress n 2nd byte 3rd byte data byte n data byte n+1 ac00044
TDA7529 electrical specifications 19/60 4 electrical specifications electrical parameters are guaranteed if f ref = 100khz, with frequency stability of +/- 20ppm max. 4.1 absolute maximum ratings 4.2 thermal data 4.3 general key parameters table 8. absolute maximum ratings symbol parameter test condition min typ max units v cc abs. supply voltage 5.5 v t amb ambient temperature range -40 105 c t stg storage temperature -55 150 c t j junction temperature 150 c table 9. thermal data symbol parameter test conditio n, comments min typ max units r thj-amb thermal resistance junction to ambient 2s2p std jedec board with thermal via underneath the component (36 board via: diameter = 0.5mm / pitch = 1.5mm), max 30% missing soldering 33 c/w table 10. general key parameters symbol parameter test conditio n, comments min typ max units v cc 5v supply voltage 4.7 5 5.35 v i cc supply current @ 5v 145 175 ma i cc_pwd supply current @ 5v in power down mode 914ma t amb ambient temperature range -40 105 c
electrical specifications TDA7529 20/60 4.4 fm - section refer to application circuit in figure 3. v cc = 4.7v to 5.35v; t amb = -40 to +105c; f c = 76 to 108 mhz; 60dbv antenna level; mono signal, unless otherwise specified. antenna level equivalence: 0dbv = 1v rms , all rf levels are intended as pd. table 11. fm - section symbol parameter test conditio n, comments min typ max units fm imr mixer and active balun g mix1 mixer conversion gain mode 1 (unloaded) 20 22 24 db mode 2 (unloaded) 14 16 18 gain attenuation range controlled by if-agc 18 20 db r in input impedance mode 1 30 50 k mode 2 5 6.5 9.5 r out output impedance active balun 15 20 30 v out_max max. output voltage without c lipping (unloaded) 122 dbv v noise input noise voltage mode1, rsource=1.5k , noiseless 33.7 nv/ hz mode 2, rsource=800, noiseless 56 iip3 3 rd order intercept point (1) mode 1 up to vin/tone = 90 dbv mode 2 up to vin/tone = 98 dbv 123 132 125 134 dbv iip2 2 nd order intercept point mode 1 mode 2 144 152 dbv irr image rejection ratio without gain/phase adjust 30 db with gain/phase adjust 40 45 fm rf agc l thr mixer input referred rf level threshold mode 1, min. setting 82 85 88 dbv mode 1, max setting 97 100 103 mode 2, min. setting 90 93 96 mode 2, max setting 105 108 111 threshold steps 4 bit control 0.5 1 1.5 db pin diode source current agc control pin 1 logarithmic current 10 ma pin diode sink current agc control pin 1 logarithmic current -3 ma pin diode source current in constant current mode 12 ma threshold shift keyed agc control input = 1v 10.5 12.5 13.5 db/v 1. parameter guaranteed by correlation.
TDA7529 electrical specifications 21/60 4.5 am - section refer to application circuit in figure 3. v cc = 4.7v to 5.35v; t amb = -40 to +105c; lw, mw and sw bands; 74dbv antenna level, unless otherwise specified. antenna level equivalence: 0dbv = 1vrms, all rf levels are intended as emf. table 12. am - section symbol parameter test conditio n, comments min typ max units am imr mixer and active balun gmix1 mixer conversion gain 7.2 9 10.5 db gmix1 gain attenuation range controlled by if-agc 18 20 db rin input impedance 5 6.5 9.5 k rout output impedance 15 20 30 w min. external load 400 w vin_max max. output voltage without clipping (unloaded) 122 dbv vnoise input noise voltage 6 8.3 nv/ hz iip3 3 rd order intercept point 130 134 dbv iip2 2 nd order intercept point 159 dbv irr image rejection ratio without gain/phase adjust 30 db irr image rejection ratio with gain/phase adjust 40 45 db am rf agc external capacitance for time constant from 1nf to 4700nf ? time constant values are directly proportional to the external capacitor value lthr mixer input referred rf level threshold min. setting 83 86 89 dbv max setting 98 101 104 threshold steps 4 bit control 0.5 1 1.5 db pin diode source current agc control pin 1 logarithmic current 10 ma min. voltage agc control pin 1 with 5a sink current 0.1 v isink 5a sink current 5 10 a pin diode source current in constant current mode 1ma max. voltage agc control pin 1 v cc - 1.4 v cc -1.2 v max. output voltage in gpo mode agc control pin 2 v dd - 0.3 v dd v min. output voltage agc control pin 2 0.3 v
electrical specifications TDA7529 22/60 4.6 if - section fast attack time constant active in case of overdrive (more than 7db) 0.05 0.5 5 ms time constant range, mode t1 range, mode t2 range, mode t3 0.5-50 2.5-250 12.5- 1250 ms ms ms table 12. am - section (continued) symbol parameter test conditio n, comments min typ max units table 13. if - section symbol parameter test condition, comments min typ max units if amplifier grange gain range input 1-3 (fm,hd,am), min. 23 25 27 db input 1-3 (fm,hd,am), max 36 38 40 input 4 (hd-radio am), min. 15 17 19 input 4 (hd-radio am), max 29 31 33 gstep gain step 3 bit control 1.5 2 2.5 db agc agc range 16.5 18 19 db agc steps 2-bit control 5.2 6 6.6 rin_input1 input impedance input 1 fm ?input @ 10.7mhz 230 330 450 w rin_input2 input impedance input 2 hd-radio fm input @ 10.7mhz 2.2 2.9 3.6 k rin_input3 input impedance input 3 am input @ 10.7mhz 7 8.2 10 k rin_input4 input impedance input 4 hd-radio am input @ 10.7mhz 78.711k rout differential output impedance 15 w vout_max max. output voltage 115 117 dbv gain, load gain variation in loaded conditions 10pf between each ifamp outputs and gnd, 10k differential load 0.5 db iip3,load iip3 decrease in loaded conditions 10pf between each ifamp outputs and gnd, 10k differential load 1db iip3 3 rd order intercept point input stage 1-3, @ 25db gain 119 122 dbv input stage 4, @ 17db gain 130 133 iip2 2 nd order intercept point input stage 1-3 142 dbv input stage 4 154
TDA7529 electrical specifications 23/60 vnoise_input 1 in1 input noise voltage @ source impedance 330 noiseless, @31db gain 3.5 4.2 nv/ hz vnoise_input 2 in2 input noise voltage @ source impedance 470 noiseless, @ 31db gain, with external 560 input termination resistor 3.8 4.6 nv/ hz vnoise_input 3 in3 input noise voltage @ source impedance 2.2k noiseless, @ 29db gain, with external 2.7k input termination resistor 56.5nv/ hz vnoise_input 4 in4 input noise voltage @ source impedance 2.2k noiseless, @ 24db gain, with external 2.7k input termination resistor 78.5nv/ hz if agc external capacitance for time constant from 10nf to 500nf in fm (asym. mode), from 100nf to 4700nf in am (sym. mode) ? time constant values are directly proportional to the external capacitor value lthr ifamp input referred fm, min. setting 88.5 91 93.5 dbv fm, max setting 99.5 101 103.5 am, min. setting 86.5 89 91.5 am, max setting 96.5 99 101.5 threshold steps 1 1.5 2 db fast attack mode in am- mode, range active in case of overdrive 0.05 0.5 5 ms time constant attack, range fm: asym. mode u1 fm: asym. mode u2 am: sym. mode s1 am: sym. mode s2 10-500 0.05-2.5 2.0-100 20-1000 s ms ms ms time constant decay, range fm: asym. mode u1 / u2 am: sym. mode s1 am: sym. mode s2 2-100 2-100 20-1000 ms ms ms table 13. if - section (continued) symbol parameter test condition, comments min typ max units
electrical specifications TDA7529 24/60 4.7 vco 4.8 reference frequency input buffer 4.9 dividers table 14. vco symbol parameter test condition, comments min typ max units frequency range vco 8% tuning range 3430 4010 mhz phase noise of lo free running vco; values referred @ 100mhz @ 10 hz @ 100 hz @ 1 khz @ 10 khz -46 -76 -103 -40 -60 -86 -106 dbc/hz deviation error fm reception, de-emphasis 50s, fnf=20hz...20khz @ min. vco frequency 8hz table 15. reference frequency input buffer symbol parameter test conditio n, comments min typ max units reference frequency input buffer mode max input voltage high 1475 mv min. input voltage low 925 mv input differential voltage 200 400 mv input impedance (xtal mode) 150 k input impedance (lvds mode) 10 k input voltage range single ended mode 200 1000 mv pp table 16. dividers symbol parameter test conditio n, comments min typ max units mixer divider v ? integer values n v divider value divider_v 7 bit 5 131 divide by 4 ? generation of 0/90/-90 lo signal for imr i/q phase error of divider phase calibration in imr -0.5 0.5 deg main divider n ? integer divider n n divider value divider_n 21bit (32/33 pre scaler) 992 2097151 reference divider r ? integer values n r divider value divider_r 8 bit 1 255
TDA7529 electrical specifications 25/60 4.10 phase locked loop 4.11 phase frequency detector and charge pump table 17. phase locked loop symbol parameter test conditio n, comments min typ max units settling time am/fm f < 0,01% @ f pfd = 100 khz 800 1200 s spurious suppression @ divided vco signal 70 db table 18. phase frequency detector and charge pump symbol parameter test conditio n, comments min typ max units pfd f pfd pfd input frequency 2 3000 khz charge pump sink current high current mode bit1 high current mode bit2 high current mode bit3 high current mode bit4 low current mode bit5 low current mode bit6 low current mode bit7 low current mode bit8 low current mode bit9 -0.4 -0.8 -1.7 -3.1 -40 -80 -160 -320 -640 -0.65 -1.3 -2.4 -4.5 -60 -120 -240 -480 -960 -0.9 -1.7 -3.1 -5.8 -80 -160 -320 -640 -1280 ma ma ma ma a a a a a source current high current mode bit1 high current mode bit2 high current mode bit3 high current mode bit4 low current mode bit5 low current mode bit6 low current mode bit7 low current mode bit8 low current mode bit9 0.4 0.8 1.7 3.1 40 80 160 320 640 0.65 1.3 2.4 4.5 60 120 240 480 960 0.9 1.7 3.1 5.8 80 160 320 640 1280 ma ma ma ma a a a a a
electrical specifications TDA7529 26/60 4.12 temperature sensor 4.13 d/a-converter 4.14 a/d-converter table 19. temperature sensor symbol parameter test conditio n, comments min typ max units temperature range -40 150 c resolution c/lsb (no direct measurement possible) 5c absolute error 15 c relative error 0.5 lsb table 20. d/a-converter symbol parameter test conditio n, comments min typ max units v out output voltage minimum value unloaded output 0.5 0.6 0.8 v output voltage maximum value unloaded output vcc ? 0.2 vcc ? 0.1 v output impedance 2 k max. output current 500 a average voltage step resolution 9bit 8.5 9 9.5 mv inl -2 2 lsb dnl -0.5 0.5 lsb conversion time @ c l =1nf 20 40 s vsrr supply voltage ripple rejection ratio 20 db table 21. a/d-converter symbol parameter test conditio n, comments min typ max units inl -2 2 lsb dnl -0.5 0.5 lsb input voltage range 0 v dd v t adc conversion time 7 s
TDA7529 electrical specifications 27/60 4.15 gpio ? general purp ose io interface pins 4.16 afsample / afhold table 22. gpio - general purpose io interface pins pin name gpio functionality multiplexed functionality details are given in the corresponding chapters gpio-output gpio-input high level low level functionality voltage voltage source current voltage sink current gp1 3.3v 1 ma 0v 1 ma analog input adc 0 ... 3.3v gp2 3.3v 1 ma 0v 1 ma analog input adc 0 ... 3.3v fm key agc input gp4 3.3v 0.1 ma 0v 10 ma am cascode v ds input 0 ... 3.3v gp5 3.3v 1 ma 0v 1 ma digital input 0 / 3.3v gp6 3.3v 1 ma 0v 1 ma digital input 0 / 3.3v spi miso output gp7 3.3v 1 ma 0v 1 ma fm-agc voltage output gp8 3.3v 1 ma 0v 1 ma am-agc voltage output symbol parameter test condition min typ max units high level output voltage @ 100k load to gnd v dd -0.3 v low level output voltage @ 100k load to v dd 0.3 v high level source current gp1 / gp2 / gp5 / gp6: @ 1k load to gnd 0.5 1 ma high level source current gp4 @ 1k load to gnd 0.08 0.1 ma low level sink current gp1 / gp2 / gp5 / gp6: @ 1k load to v dd 0.8 1 ma low level sink current gp4: @ 100 load to v dd 8.0 10 ma input impedance digital input mode 100 k input voltage range gp1 / gp2 0 3.5 v high level input voltage gp5 / gp6 used as digital input 2.2 3.5 v low level input voltage gp5 / gp6 used as digital input -0.05 1.0 v table 23. afsample / afhold symbol parameter test conditio n, comments min typ max units output voltage at afsample/afhold 3.6 v maximum sink current v o = 0.4v 800 a
electrical specifications TDA7529 28/60 4.17 serial data interface table 24. serial data interface symbol parameter test condition, comments min typ max units vdd supply voltage 2.7 3.5 v f clk clock frequency guaranteed range @ spi guaranteed range @ i 2 c 4 1 mhz mhz power on delay time ready for communication after power-on-reset 10 ms high level output voltage output signals v dd -0.3 v dd v low level output voltage output signals -0.05 0.3 v high level source current output signals 0.08 0.1 ma low level sink current output signals 0.8 1 ma rise / fall time output signals, 90% 15 25 40 ns high level input voltage input signals, except as 2.0 3.5 v low level input voltage input signals, except as -0.05 1.0 v high level input voltage as input signal 2.2 3.5 v medium level input voltage as input signal 1.1 1.7 v low level input voltage as input signal -0.05 0.6 v input impedance input signals 100 k power-on impedance all signals 100 k rise / fall time input signals except clk, min. acceptable duration range, 90% 0.01 1000 s input signal clk, min. acceptable duration range, 90% 0.01 10 s
TDA7529 tuning state machine 29/60 5 tuning state machine frequency changes in a system employing the TDA7529 can be efficiently performed using a built-in state machine which simplifies the microprocessor supervisory functions. the state machine, which can work in 8 different modes, can be invoked by a simple write operation into the tuner registers and, provided that the frequency to be jumped to has been pre- loaded into the front-end registers through a previous separate or is loaded through a concurrent write operation, the fe jump sequence is automatically managed and flags are provided to the back-end to indicate the current condition. 5.1 tuning state machine modes hereafter the description of the 8 modes can be found. they are chosen by byte 12 bits<6:4>. the diagrams depicting the fe and flag conditions for each of the 8 modes are as follows: 5.1.1 mode 000: buffer (nil) when this mode is selected, no action is undertaken by the state machine. 5.1.2 mode 001: preset figure 8. preset timing diagram this mode is used to jump to a different frequency and stay there, with reception at the end of the sequence. afsample can be used to tell the back-end when to mute and to unmute the audio output. the 60 ms mute time (programmable) after the pll has reached the locked condition can be used to check the rds signal presence a nd content in addition to the analog quality information. afhold can be used to tell the back-end to switch to faster time constants for quick quality acquisition. events time transmission with subaddr. bit 7 = 1 wait t 1ms wait for t plllock wait 50 us wait t 60ms afsample afhold b.e. operation mute audio quality dets in fast mode unmute audio bus stop event regs swap ac0004 5
tuning state machine TDA7529 30/60 5.1.3 mode 010: search figure 9. search timing diagram this mode is used to jump to a different frequency and stay there, with audio muted. afsample can be used to tell the back-end when to mute the audio output. afhold can be used to tell the back-end to switch to faster time constants for quick quality acquisition. 5.1.4 mode 011: af update figure 10. af update timing diagram this mode is used to jump to an af frequency, check its quality, jump back to the starting frequency and continue reception. afsample can be used to tell the back-end when to acquire the af frequency quality. afhold can be used to tell the back-end to mute/unmute the audio and keep normal processing on hold. events time transmission with subaddr. bit 7 = 1 wait t 1ms wait for t plllock wait 50 us afsample afhold b.e. operation mute audio quality dets in fast mode bus stop event regs swap ac0004 6 events time transmission with subaddr. bit 7 = 1 afsample afhold b.e. operation mute audio hold unmute audio bus stop event regs swap regs swap freeze af qual ac0004 7
TDA7529 tuning state machine 31/60 5.1.5 mode 100: jump figure 11. jump timing diagram this mode is used to jump to a different frequency and stay there, with reception at the end of the sequence. afhold can be used to tell the back-end to mute/unmute the audio and keep normal processing on hold. afsample can be used to tell the back-end when the quality signal processing can be restarted, with a stable situation to start from. 5.2 mode 100: check figure 12. check timing diagram this mode is used to jump to a different frequency and stay there, with audio muted. afhold can be used to tell the back-end to mute/unmute the audio and keep normal processing on hold. afsample can be used to tell the back-end when to freeze the quality signal processing. events time transmission with subaddr. bit 7 = 1 wait t 1ms wait for t plllock wait t 0.5ms wait 50 us afsample afhold b.e. operation mute audio hold unmute audio bus stop event regs swap ac0004 8 events time transmission with subaddr. bit 7 = 1 wait t 1ms wait for t plllock afsample afhold b.e. operation mute audio hold bus stop event regs swap ac0004 9
tuning state machine TDA7529 32/60 5.3 mode 110: load figure 13. load timing diagram the content of the buffer and control registers is swapped. no transition occurs on the afhold and afsample lines. 5.4 mode 111: end figure 14. end timing diagram this mode is used to end sequences that te rminate with muted audio, after the decision on whether to stay to that frequency or jump to a different one has been taken. afhold can be used to tell the back-end to unmute the audio. afsample can be used to tell the back-end to restore normal quality signal processing. most of the wait times of the algorithm can actually be programmed. the following table summarizes the minimum, maximum and default values of the programmable wait times. the indicated values are valid only for the advised configuration where the phase detector reference frequency is 100 khz. events time transmission with subaddr. bit 7 = 1 bus stop event regs swap ac0005 0 events time transmission with subaddr. bit 7 = 1 wait 50 us afsample afhold b.e. operation unmute audio bus stop event ac00051
TDA7529 tuning state machine 33/60 5.5 register swap some of these modes contain one or two register "swap" operation(s). the changes within the register structure during a swap operation depend on the operating mode of the chip. if the chip is programmed in the "buffer/control" mode (chosen by setting byte 12 bit 7 = 1), which is necessary to take advantage of the tuning state machine, it is suggested that the microprocessor write data only in the normal register bank (bytes from 16 to 31), because the state machine itself takes care of exchanging the content of the normal register bank with that of the shadow bank (bytes from 32 to 47) during a swap. the normal registers are intended to be written to by the radio microprocessor, whereas the registers that actually control the device circuits are the shadow ones. in any case it is suggested that the bits 5 and 4 of byte 0, that define which control bank is actually used to drive the device circuits, should not be touched after setting them to 0 after reset because they are automatically updated by the tuning state machine. table 25. values of the programmable wait times parameter name register value time t plllock byte 15 bits<7:3> min. 00000 20 us default 00110 1 ms maximum 11111 5 ms t 0.5ms byte 30 bits<7:2> min. 000000 70 us default 000101 0.5 ms maximum 111111 5 ms t 1ms byte 20 bits<7:2> min. 000000 10 us default 001100 1 ms maximum 111111 5 ms t 2ms byte 29 bits<7:2> min. 000000 50 us default 011000 2 ms maximum 111111 5 ms t 60ms byte 04 bits<7:3> min. 00000 1 ms default 10111 60 ms maximum 11111 80 ms
tuning state machine TDA7529 34/60 5.6 state machine start the tuning state machine is activated only at the end of the transmission if bit 7 of the subaddress is 1. the activation sequence, therefore, is to be done in the following way. figure 15. buffer/control serial bus sequence start address (if i2c) subaddress regs 0:31 stop bit 7 = 1 reg 12 bit 6:4 sets desired state machine mode sets f2 into buffer registers tuning state machine starts ac00052
TDA7529 registers description 35/60 6 registers description figure 16. registers description no name r/w msb (7) 6 5 4 3 2 1 lsb (0) power on default 0 short reg r/w x x shagc shpll adcen gpioen pwr 00h 1 adcctrl r/w adcclk adcs2 adcs1 adcs0 rcenable adcautomode temp_pwr 00h 2 gpioval r/w gpo8_amagcv gpo7_fmagcv gpio6_miso gpio5_aout gpo4_amcas cp_curr_switch gpio2io gpio1io 00h 3 agcmixctrl r/w ifin1_am_fm keyagcen fmagcpwr amagcpwr mixinfmam balunoutimp mixout1 mixout2 00h 4 misc1 r/w wait60ms(4) wait60ms(3) wait60ms(2) wait60ms(1) wait60ms(0) disvcc plltest amagc_isink 00h 5 divr r/w divr7 divr6 divr5 divr4 divr3 divr2 divr1 divr0 00h 6 ifagc_sh r/w ifagc_fm_am ifagcthr2 ifagcthr1 ifagcthr0 gpio5 output ifsection_pwr 00h 7 fmagc r/w fmthr3 fmthr2 fmthr1 fmthr0 fmagcmodec1 fmagcmodec0 fmagcmodev1 fmagcmodev0 00h 8fm_am_vthr r/w amagcfat afh_mux vthr5 vthr4 vthr3 vthr2 vthr1 vthr0 00h 9 mixalign1 r/w ifamp_ictrl2 ifamp_ictrl1 iredh iredl casc_ctrl imrf2 imrf1 imrf0 00h 10 mixalign2 r/w imrph3 imrph2 imrph1 imrph0 imrg3 imrg2 imrg1 imrg0 00h 11 pllctrl r/w dz4 dz3 dz2 dz1 cpcur_800u swfref divren pllpwr 00h 12 pllctrl2 r/w func mode2 mode1 mode0 ds4 ds3 ds2 ds1 00h 13 plltest r/w pol pfd_d1 pfd_d0 pllt4 pllt3 pllt2 pllt1 pllt0 00h 14 misc2 r/w ifagcin4ctrl ensmooth reg48sel ifamp_ictrl0 rcfreq_1 rcfreq_0 vcomag1 vcomag0 00h 15 wait_lock r/w wait lock(4) wait lock(3) wait lock(2) wait lock(1) wait lock(0) divvtest vcoext lock_bit 00h 16 agctc_a r/w ifagctcam ifagctcfm amtc1 amtc0 fmtc3 fmtc2 fmtc1 fmtc0 00h 17 amagc_a r/w amthr3 amthr2 amthr1 amthr0 amagcmodec1 amagcmodec0 amagcmodev1 amagcmodev0 00h 18 gpiom_a r/w gpo8hl gpo7hl gpio6hl gpio5hl gpo4hl gpio2hl gpio1hl 00h 19 ifctrl_a r/w ifin0_std_iboc ifampgaina2 ifampgaina1 ifampgaina0 mixinfm amagcinbuffer rctest 00h 20 r/w wait1ms(5) wait1ms(4) wait1ms(3) wait1ms(2) wait1ms(1) wait1ms(0) 00h 21 divn_a1 r/w divna20 divna19 divna18 divna17 divna16 divna15 divna14 divna13 00h 22 divn_a2 r/w divna12 divna11 divna10 divna9 divna8 divna7 divna6 divna5 00h 23 divn_a3 r/w divna4 divna3 divna2 divna1 divna0 00h 24 divv_a r/w vco1r divva6 divva5 divva4 divva3 divva2 divva1 divva0 00h 25 cpcur_a r/w cpah3 cpah2 cpah1 cpah0 cpal3 cpal2 cpal1 cpal0 00h 26 dac1_a r/w dac1a8 dac1a6 dac1a5 dac1a4 dac1a3 dac1a2 dac1a1 dac1a1 00h 27 dac2_a r/w dac2a8 dac2a6 dac2a5 dac2a4 dac2a3 dac2a2 dac2a1 dac2a1 00h 28 pll_dac_a r/w iqsela vcosw dac2a0 dac1a0 dac2off dac1off 00h 29 misc4_a r/w wait2ms(5) wait2ms(4) wait2ms(3) wait2ms(2) wait2ms(1) wait2ms(0) min16 00h 30 r/w wait0.5ms(5) wait0.5ms(4) wait0.5ms(3) wait0.5ms(2) wait0.5ms(1) wait0.5ms(0) agctest1 agctest0 00h 31 r/w if test adc test adcdac5 adcdac4 adcdac3 adcdac2 adcdac1 adcdac0 00h 32 agctc_b r/w 00h 33 amagc_b r/w 00h 34 gpiom_b r/w 00h 35 ifctrl_b r/w 00h 36 amfilt_b r/w 00h 37 divn_b1 r/w 00h 38 divn_b2 r/w 00h 39 divn_b3 r/w 00h 40 divv_b r/w 00h 41 cpcur_b r/w 00h 42 dac1_b r/w 00h 43 dac2_b r/w 00h 44 pll_dac_b r/w 00h 45 misc4_b r/w 00h 46 00h 47 00h 48 read_status r lock gpio6r gpio5r maskmetal1 maskmetal0 maskset1 maskset0 00h 49 read_adc r adcok adc5 adc4 adc3 adc2 adc1 adc0 00h this byte is valid on the output if bit shagc is set to '1', otherwise byte nr. 16 is valid on the output all bytes from 33 to 45 are valid on the output if shpll is set to '1', otherwise byte 17 to 29 are valid on the output adcstart
registers description TDA7529 36/60 6.1 data byte specification 6.1.1 short_reg (0) table 26. short_reg (0) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 global pwr power down the ic power on the ic 0 1 gpio enable all gpio in tristate all gpio enable 0 1 adcen 6bit adc on 6bit adc off 0 1 adcstart no conversion starts a single ad conversion 0 1 shpll pll register from 17 to 31 are valid pll register from 33 to 47 are valid 0 1 shagc agc tc register 16 is valid agc tc register 32 is valid x not used x not used
TDA7529 registers description 37/60 6.1.2 adcctrl (1) table 27. adcctrl (1) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 temperature sensor power enabled disabled 0 1 adc auto mode automatic restart disable automatic restart enable 0 1 rc oscillator enable enable disable x adcstart (like bit 0.3) 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 adc input selection temp sensor fm agc am agc if agc vco tuning voltage (3/5 * vtune) gp1 gp2 2/5 * vcc 0 1 adc clock selection adc clock source = rc osc adc clock source = refdiv output
registers description TDA7529 38/60 6.1.3 gpio mode (2) table 28. gpio mode (2) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 gpio1 input / output analog input to ad converter digital output 0 1 gpio2 input / output analog input to ad converter digital output 0 1 cp current switch automatic switch disabled automatic switch enabled 0 1 gpio4 input / output analog input digital output 0 1 gpio5 input / output digital input output (analog or digital) 0 1 gpio6 input / output digital input (or miso output in spi mode) digital output (or miso output in spi mode) 0 1 gpio7 input / output fm agc voltage output digital output 0 1 gpio8 input / output am agc voltage output digital output
TDA7529 registers description 39/60 6.1.4 agc and mixer control (3) table 29. agc and mixer control (3 msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 1 0 1 mixout 1 / 2 all off = power down mixer section mixout 1 active mixout 2 active forbidden state 0 1 balun output drive capability low drive capability high drive capability 0 1 mixer input fm / am selection am input active fm input active 0 1 am agc on / off off on 0 1 fm agc on / off off on 0 1 keyed agc enable keyed agc off keyed agc on 0 1 if input selection fm / am if input am if input fm
registers description TDA7529 40/60 6.1.5 register (4) 6.1.6 divider r (5) table 30. register (4) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 amagc isink (2ma fixed current) off on 0 1 plltest off on 0 1 disvcc por activated from ifvcc por non activated from ifvcc 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 wait60ms 1ms (min. value) 60ms (default value) 80ms (max value) table 31. divider r (5) msb lsb divider r value d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x divider r value divr0 : : divr7
TDA7529 registers description 41/60 6.1.7 if agc control (6) table 32. if agc control (6) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 if section on / off off on 0 1 gpio 5 output mode off on = gpio 5 analog output enable xx not used 0 0 : : 1 0 0 : : 1 0 1 : : 1 if agc threshold if output level = 89dbv(am) / 91dbv (fm) if output level = 90.5d bv(am) / 92.5dbv (fm) : : if output level = 99dbv(am) / 101dbv (fm) 0 1 if agc mode fm / am selection fm mode am mode
registers description TDA7529 42/60 6.1.8 fm agc (7) table 33. fm agc (7) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 1 0 1 voltage output mode off n/a calibration mode voltage output on 0 0 1 1 0 1 0 1 current output mode off constant 2ma output positive current output neg. / pos. current output 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fm agc threshold mixer input level = 93dbv (fm1) / 97dbv (fm2) mixer input level = 94dbv (fm1) / 98dbv (fm2) mixer input level = 95dbv (fm1) / 99dbv (fm2) mixer input level = 96dbv (fm1) / 100dbv (fm2) mixer input level = 97dbv (fm1) / 101dbv (fm2) mixer input level = 98dbv (fm1) / 102dbv (fm2) mixer input level = 99dbv (fm1) / 103dbv (fm2) mixer input level = 100dbv (fm1) / 104dbv (fm2) mixer input level = 93dbv (fm1) / 97dbv (fm2) mixer input level = 92dbv (fm1) / 96dbv (fm2) mixer input level = 91dbv (fm1) / 95dbv (fm2) mixer input level = 90dbv (fm1) / 94dbv (fm2) mixer input level = 89dbv (fm1) / 93dbv (fm2) mixer input level = 88dbv (fm1) / 92dbv (fm2) mixer input level = 87dbv (fm1) / 91dbv (fm2) mixer input level = 86dbv (fm1) / 90dbv (fm2)
TDA7529 registers description 43/60 6.1.9 agc voltage threshold (8) 6.1.10 mixer al ignment 1 (9) table 34. agc voltage threshold (8) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 : : 1 1 0 0 : : 1 1 0 0 : : 1 1 0 0 : : 1 1 0 0 : : 1 1 0 1 : : 0 1 transfer voltage from voltage out to current out 200mv 237.5mv : : 2.5625v 2.6v 0 1 am fast attack off on table 35. mixer alignment 1 (9) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 : 1 : 1 0 0 : 0 : 1 0 1 : 0 : 1 iq-filter frequency adjust +2.4mhz +1.8mhz : 0 : -1.8mhz 0 1 cascode control loop on / off on off 0 0 1 1 0 1 0 1 mixers current control normal bias low reduction high reduction n/a 0 0 1 1 0 1 0 1 ifamp driving capability normal intermediate 1 intermediate 2 high
registers description TDA7529 44/60 6.1.11 mixer al ignment 2 (10) table 36. mixer alignment 2 (10) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 : 0 1 : 1 1 1 1 1 : 0 0 : 1 1 1 1 0 : 0 0 : 1 1 1 0 1 : 0 0 : 0 1 iq-filter gain adjust -0.7db -0.6db -0.5db : 0db 0db : +0.6db +0.7db 0 0 0 0 0 : 0 1 1 1 1 1 : 1 1 0 0 0 0 1 : 1 0 0 0 0 1 : 1 1 0 0 1 1 0 : 1 0 0 1 1 0 : 1 1 0 1 0 1 0 : 1 0 1 0 1 0 : 0 1 iq-filter phase adjust 0 +0.2 deg +0.2 deg +0.4 deg +0.6 deg : +1.2 deg -1.2 deg -1.0 deg -1.0 deg -0.8 deg -0.6 deg : -0.2 deg 0
TDA7529 registers description 45/60 6.1.12 pll control 1 (11) 6.1.13 pll control 2 (12) table 37. pll control 1 (11) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 pll enable pll off pll on 0 1 divider r enable divider r off; = div / 1 divider r on 0 1 select reference input reference frequency input = lvds reference frequency input = xtal 0 1 charge pump current 800 a 0 a 800 a 0 : 1 0 : 1 0 : 1 0 : 1 slope of high current cp highest : lowest table 38. pll control 2 (12) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 : 1 0 : 1 0 : 1 0 : 1 delay of high current cp shortest : longest 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 state machine modes decode buffer mode preset search af update jump check load end 0 1 register functionality control normal/shadow mode buffer/control mode
registers description TDA7529 46/60 6.1.14 pll test (13) 6.1.15 misc 2 (14) table 39. pll test (13) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xx10 pll test set to default 01 pfd default 0 pfd polarity table 40. misc 2 (14) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 1 0 1 vco magnitude 1v 2v 3v 4v 0 0 1 1 0 1 0 1 oscillation frequency of rc oscillator 0.68 mhz 1.31 mhz 1.92 mhz 2.49 mhz 0 1 ifamp current control normal bias high current mode bias 0 1 reg48sel shagc and shpll on d48<1:0> maskmetal and maskset on d48<1:0> 0 1 ensmooth smooth disabled smooth enabled 0 1 ifagc control when in4 selected normal thresholds shift
TDA7529 registers description 47/60 6.1.16 wait lock (15) 6.1.17 agc time cons tant settings (16 / 32) table 41. wait lock (15) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 1 0 1 test d18<0> lock_bit cmpout vdivout 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 wait lock 0.04ms (min. value) 1ms (default value) 5.08ms (default value) table 42. agc time constant settings (16 / 32) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 fm agc decay time constant d1 d2 d3 0 0 1 0 1 0 fm agc attack time constant a1 a2 a3 0 0 1 0 1 0 am agc time constant t1 t2 t3 0 1 if agc time constant fm u1 u2 0 1 if agc time constant am s1 s2
registers description TDA7529 48/60 6.1.18 amagc control (17 / 33) table 43. amagc control (17 / 33 msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 1 0 1 am agc voltage output mode off voltage output / sense internal calibration voltage output / sense external 0 0 1 1 0 1 0 1 am agc current output mode off constant 2ma positive current n/a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 am agc thresholds mixer input level = 94 dbv mixer input level = 95 dbv mixer input level = 96 dbv mixer input level = 97 dbv mixer input level = 98 dbv mixer input level = 99 dbv mixer input level = 100 dbv mixer input level = 101 dbv mixer input level = 94 dbv mixer input level = 93 dbv mixer input level = 92 dbv mixer input level = 91 dbv mixer input level = 90 dbv mixer input level = 89 dbv mixer input level = 88 dbv mixer input level = 87 dbv
TDA7529 registers description 49/60 6.1.19 gpio output level control (18 / 34) 6.1.20 if control (19 / 35) table 44. gpio output level control (18 / 34) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 : x : : x : : x : : x : : x : 0 1 0 1 gpiox high / low output level gpio1 low gpio1 high gpio2 low gpio2 high : gpiox low / high : gpio8 low gpio8 high table 45. if control (19 / 35) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x not used 0 1 rc test test enabled test disabled 0 1 amagc input buffer buffer enabled buffer disabled 0 1 mixer input selection for fm fm1 mixer input fm2 mixer input 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 if amplifier gain 25db (input1-3) / 19db (input4) 27db (input1-3) / 21db (input4) : 37db (input1-3) / 31db (input4) 39db (input1-3) / 33db (input4) 0 1 if input selection analog / iboc iboc analog
registers description TDA7529 50/60 6.1.21 af state machi ne wait time 1 (20 / 36) 6.1.22 pll main divider (n-divider) 1 (21 / 37) 6.1.23 pll main divider (n-divider) 2 (22 / 38) table 46. af state machine wait time 1 (20 / 36) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x not used x not used 0 0 0 0 0 1 0 1 0 0 0 0 wait 1ms 0.04ms (min. value) 1ms (default value) table 47. pll main divider (n-divider) 1 (21 / 37) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x x x x divider n value m8 m9 m10 m11 m12 m13 m14 m15 table 48. pll main divider (n-divider) 2 (22 / 38) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x x x x divider n value m0 m1 m2 m3 m4 m5 m6 m7
TDA7529 registers description 51/60 6.1.24 pll main divider (n-divider) 3 (23 / 39) 6.1.25 pll divider ratio calculation 6.1.26 vco divider (v-divider) (24 / 40) table 49. pll main divider (n-divider) 3 (23 / 39) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x divider n value a0 a1 a2 a3 a4 table 50. pll divider ratio calculation m counter a counter notes m16 m15 ? m7 ? m1 m0 a4 a3 a2 a1 a0 n= 32*p + a m=32 n= m*p + a m>32 (p=32) table 51. vco divider (v-divider) (24 / 40) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x x x divider v value v0 v1 v2 v3 v4 v5 v6 0 1 vco range selection range 2 range 1
registers description TDA7529 52/60 6.1.27 charge pump current (25 / 41) 6.1.28 tuning dac 1 (26 / 42) table 52. charge pump current (25 / 41) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x low current charge pump 50 a 100 a 200 a 400 a x x x x high current charge pump 0.5 ma 1ma 2ma 4ma table 53. tuning dac 1 (26 / 42) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x x x x dac 1 voltage 8..1 dac1_. dac1_2 dac1_3 dac1_4 dac1_5 dac1_6 dac1_7 dac1_8
TDA7529 registers description 53/60 6.1.29 tuning dac 2 (27 / 43) 6.1.30 dac output voltag e = 600mv + dacval * 9mv 6.1.31 different controls (28 / 44) table 54. tuning dac 2 (27 / 43) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x x x x dac 2 voltage 8..1 dac2_1 dac2_2 dac2_3 dac2_4 dac2_5 dac2_6 dac2_7 dac2_8 table 55. different controls (28 / 44) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 dac 1 on / off off on 0 1 dac 2 on / off off on x dac 1_0 x dac 2_0 xx not used x not used 0 1 iq phase select i anticipates q q anticipates i
registers description TDA7529 54/60 6.1.32 misc 3 (29 / 45) 6.1.33 analog test select (30 / 46) table 56. misc 3 (29 / 45) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x pll n divider msb m16 x not used 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 0 1 1 wait 2ms 0.08ms (min. value) 2ms (default value) 5.04ms (default value) table 57. analog test select (30 / 46) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 1 0 1 analog test outp ut signal select if agc fm agc amagc dac voltage of adc 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 wait 0.5ms 0.02ms (min. value) 0.5ms (default value) 5.06ms (max value)
TDA7529 registers description 55/60 6.1.34 ad converter test (31 / 47) 6.1.35 read 1 (48) table 58. ad converter test (31 / 47) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x x adc dac direct programming dac 0 dac 1 dac 2 dac 3 dac 4 dac 5 0 1 adc test enable off on 0 1 agc test enable off on table 59. read 1 (48) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 1 0 1 mask set revision a b c d 0 0 1 1 0 1 0 1 metal mask revision a b c d 0 1 gpio 5 level low high 0 1 gpio 6 level low high
registers description TDA7529 56/60 6.1.36 read 2 (49) table 60. read 2 (49) msb lsb function d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 x x x x x x ad converter result adc0 adc1 adc2 adc3 adc4 adc5 0 1 ad converter result status not ok ok
TDA7529 application schematic 57/60 7 application schematic figure 17. application schematic vpll_5v vcc_5v sda scl vdig_5v vrf_5v vrf_5v amant ifout1 ifout2 vcc_5v scl miso fmant csn ifout2 ifout1 fmant sda dac1/dac2 vpll_5v refp refn ifagc1 ifagc2 afsa mple afhold afhold afsample vdig_5v amant vrf_5v dac1/dac2 fmagc2/gp7 gp1 ifagc2 gp2/key gp5 ifagc1 refn refp vcc_5v balun rf rf rf rf rf rf rf rf vco vco pll pll balun balun if if bus rf bus if ro vco bus pll balun ro rf rf rf rf ro if if if rf c45 68pf c13 100nf d3 kv1770r toko 1 2 3 r15 220 c52 100nf c39 22uf c33 100nf c69 22uf c38 100nf r11 2k l4 blmm18bd102sn1 murata r9 27 r4 1.5k 3 r1 330 c35 100nf l3 llq2012-fr39 toko 390 nh r16 1m c71 22uf c1 100nf c27 10nf c26 18pf c37 100nf l2 llq2012-fr33 toko 330 nh c15 10nf c32 1nf c30 5.6pf c21 22uf l5 180nh toko llq2012-fr18 c24 8.2pf r8 22k c48 220pf c23 22uf c18 100nf l7 1mh 4 c20 12pf 2 l11 llq2012-fr33 toko 330 nh c16 39pf r13 10k l9 68uh murata lq2mcn680k02b d4 bar14-i infineon 2 1 3 d2 kp2311e toko 2 1 l20 blmm18bd102sn1 murata c43 22nf c29 100nf c14 2.2uf r6 220 c22 680pf c49 1uf l8 blm18d102sni murata c19 100nf c10 100nf c9 100nf r14 100 l6 toko e558hn-100101 93 nh c28 xxx c34 22pf c76 22uf l1 blmm18bd102sn1 murata c6666 22uf j1 con29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 c70 22uf c17 100nf q1 hn3g01j thoshiba 3 4 5 1 2 c46 4.7nf c25 22uf r12 4.7k c5 100nf c40 100nf d1 kp2311e toko 2 1 r10 390 c53 100nf c11 680pf 1 l10 68uh murata lq2mcn680k02b r5 220 c8 1uf u1 TDA7529 1 2 3 4 5 6 17 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 balun1 balundec dac2 dac1 fmmix1in fmmix1dec ifagc2 gndif balunout2 balunout1 vccrf2 tcfm tcam gndrf2 gp5 ifin1 gp2/key ifin2 biasd1 ifin3 vccif ifin4 ifdec tcif2 fmagc2/gp7 fmagc1 fmmix2in fmmix2dec gndrf1 amagc1 ammixdec ammixin mixbiasdec ifagc1 gp4/vds amagc2/gp8 afhold afsample vccrf1 vcodec1 vtune vcodec2 vcognd lflc lfhc gndpll vccpll gp1 gndro tcif1 ifout1 ifout2 biasd2 vdddec vccbus miso/gp6 mosi clk cs/as ps gndbus vccro xtalo xtali l12 10uh murata lqm18fn100m00b c42 10nf c12 10nf c44 220nf r3 220 c4 100nf c6 22nf c47 33pf c36 1nf c51 2.2uf xt1 sfel10m7 murata r2 100 r7 68k c7 1uf c50 100nf ac00053
package information TDA7529 58/60 8 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 18. lqfp64 (10x10x1.4mm) exposed pad down mechanical data and package dimensions (exposed pad size for d2 and e2: 4.5mm max.) outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d2 according to pad size d3 7.500 0.2953 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3858 0.3937 0.4016 e2 according to pad size e3 7.500 0.2953 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 3.500 7.000 0.1378 0.2756 ccc 0.080 0.0031 note: 1. exact shape of each corner is optional. lqfp64 (10x10x1.4mm) exposed pad down 7278841 c
TDA7529 revision history 59/60 9 revision history table 61. document revision history date revision changes 7-mar-2007 1 initial release.
TDA7529 60/60 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of TDA7529

	To Download TDA7529 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .